1. Field of the Invention
This invention relates to random access memory (RAM) arrangements. More particularly, the invention relates to such arrangements in which data are written into and read out of a RAM asynchronously.
2. Description of the Prior Art
Where data are being written into and read out of a RAM synchronously the RAM can be supplied with a signal representing the data to be written in, a signal comprising a sequence of write addresses, a signal comprising a sequence of read addresses, a write control signal and a read control signal. The read control signal is normally a clock pulse signal with a 50% duty ratio and the period of the data signal and of the read and write address signals is equal to the period of the clock pulse signal. The write control signal is similar, but of the opposite phase. In the first half of each period of the read control signal, therefore, data are read from the RAM under control of the read control signal and in dependence on the corresponding read address. In the second half of each period of the write control signal, data are written into the RAM under control of the write control signal and in dependence on the corresponding write address. Delay in accessing addresses and in recovery after read-out result in short unusable intervals at each transition between reading and writing, but there is a clear interval during each read-out period in which the data to be read out can be derived.
The situation becomes more difficult, however, when read out and write in are not in synchronism. This occurs, for example, in time base correction of a television signal read out from a video tape recorder (VTR) and containing timing instabilities. It also occurs in processing a television signal prior to recording the signal on a VTR, for example, where digital data derived at a frequency related to the colour sub-carrier frequency is converted to data at a frequency related to the line frequency. This may involve conversion from say 8.86 Megahertz to 8.00 Megahertz. In both these cases, and in other applications, asynchronous access to a RAM is necessary. The problem is compounded by the use of larger RAMs which, although inherently advantageous due to their ability to store large amounts of data, are somewhat inflexible.